1. Field of the Invention
This invention relates to an improved interlayer insulating film or passivation film used in a semiconductor device.
2. Description of the Prior Art
FIG. 1 is a cross-sectional illustration of an insulating film formed by using the conventional CVD (chemical vapor deposition) method. In FIG. 1, an interconnection 2 of, e.g., Al is formed on a semiconductor substrate 1 and an insulating film 4 is formed by using the CVD method to cover the semiconductor substrate 1 and Al interconnection 2. As can be clearly seen in FIG. 1, when an insulating film is formed by using the CVD method, it often happens that the coverage of the insulating film 4 is poor, and further, necking takes place in step portions. This drawback is peculiar to the CVD method and could be remedied to some extent by suitably selecting the film forming conditions, but cannot be completely eliminated, forming the greatest obstacle to the formation of multilayer interconnections and the like. Thus, the bias sputtering method has been invented to eliminate the aforesaid drawback peculiar to the CVD method.
FIG. 2 is a cross-sectional illustration of an insulating film formed by using the bias sputtering method. In FIG. 2, after an Al interconnection 2 has been formed on a semiconductor substrate 1, a flat insulating film 3 is formed by using the bias sputtering method to cover the semiconductor substrate 1 and Al interconnection 2. As can be seen in FIG. 2, the insulating film forming method using the bias sputtering method is an epochal one capable of perfectly planarizing the insulating film 3 under particular conditions even if there are step portions due to the presence of the Al interconnection 2. Particularly where the width of the interconnection 2 is less than twice the thickness of an insulating film to be formed thereon, perfect planarization of the insulating film 3 is possible. The bias sputtering method consists in performing sputter etching by applying a bias voltage to the substrate 1 while performing deposition of the film according to the usual sputtering method. In this case, since the sputter etching is higher in etching rate at step portion than at the planar portion, the apparent deposition rate for step portions seems low, and a planar film is thus formed. The mechanism of planarization of insulating films by the bias sputtering method is described in "Study of Planarized Sputter-Deposited SiO.sub.2 " by C. Y. Ting et al., Journal of Vacuum Science and Technology, Vol. 15, No. 3, May/June, 1978, pp. 1105-1112.
The process of forming a planar insulating film by the bias sputtering method will now be described.
FIG. 3 is a sectional view showing the process of forming insulating films by the bias sputtering method. As can be seen in FIG. 3, in the bias sputtering method, insulating films are successively formed on an Al interconnection 2 as indicated by reference numerals 51 through 54. In this connection, if the pattern width of the Al interconnection 2 is small, as shown in FIG. 2, the insulating film can be easily planarized even if the insulating film is not deposited so thick on the Al interconnection 2. However, in the bias sputtering method, planarization of insulating films is proceeded in such a manner that the width of the underlying pattern to be covered is gradually decreased, as indicated by the reference numerals 51 through 54. Therefore, as shown in FIG. 4, if a wide Al interconnection 2 such as a power supply line is an underlying pattern to be covered, for perfect planarization of an insulating film 3 to be formed by the bias sputtering method it has been necessary that the film be sufficiently thick. To eliminate this drawback, a method has been proposed in which if the underlying pattern to be covered is wide, sputtering is performed by changing the substrate bias voltage midway through the process.
A method of forming planar insulating films using a two-step RF bias sputtering method is disclosed in Japanese Patent Application Laid-Open No. 200440/1984, applied for patent Apr. 28, 1983 by T. Mogami et al., "Method of Manufacturing an Interconnection Structure", and "SiO.sub.2 Planarization by RF Bias Sputtering" by T. Mogami, 25th Symposium on Semiconductor Integrated Circuits Technique, Dec. 26, 1983.
The method of forming planar insulating films by the two-step RF bias sputtering method will now be described.
FIG. 5 is a view showing the process of formation of insulating layers by the bias sputtering method when a pattern is wide. In FIG. 5, a wide Al interconnection 2 is formed on a semiconductor substrate 1, and an interlayer insulating film 3 is formed thereon. This improved method will now be described with reference to FIG. 5. First, an oxide film 3 is formed by the bias sputtering method with a relatively low substrate bias voltage applied. At this time, as indicated by the reference numeral 61, there is formed an insulating film having a smoother coverage than that obtained by using the CVD method.
Then, the bias voltage is increased so that in the planar portion the rate of deposition by sputtering is equal to the rate of sputter removal. As a result, seemingly, there is neither deposition nor removal taking place in the planar portion, whereas in the step portions the sputter removal rate is higher than the sputter deposition rate, so that as indicated by the reference numerals 61 through 64 the removal proceeds to make planarization of insulating films possible. Even with this method, however, if the pattern width of the Al interconnection 2 is large, it takes a long time to planarize the insulating film and hence the time required to process one wafer or the like is very long; thus, the processing capacity has substantially been limited.
On the other hand, to increase the processing capacity, if the film is left as it is in the state shown at 61 in FIG. 5, then the step portion of the pattern of the Al interconnection 2 will have a thin region 7 of small effective thickness formed therein as shown in FIG. 6, leading to dielectric breakdown etc., which has been an obstacle to usage.
As described above, in the conventional bias sputtering method, though the coverage of the insulating film being formed is improved, perfect planarization of the insulating film being formed makes it necessary to increase the film thickness or to change the bias condition midway through the process for sputtering.
If insulating films are deposited to the thickness usually required of the planar portion by simply using the bias sputtering method, thin film portions are formed locally and particularly in the step portions, where dielectric breakdown will take place, which has been a problem in use.